I'm primarily an analog and logic designer, so please bear with my lack of DSP chops. I've got an application where I'm looking to feed a DAC at a constant 128 MSPS from a data stream that will be a power of 2 fraction of that (64 MSPS down to 250 kSPS). I'd like to be able to get pretty close to the Nyquist limit (say 0.4 or so) of whatever the original data rate is. It seems so far like my two primary choices for interpolating the data up are: a) a CIC filter plus an FIR precompensator to clean up the sinc response of the CIC, followed by a barrel shifter to get rid of the bit growth or b) a single (or possibly a cascade of?) FIR interpolation filters. The implementation platform will be a Spartan-6 FPGA, which means my primary DSP tool is a dedicated multiply+add block, which can of course be configured as a multiply+accumulate. Ultimately, the DAC feeds a fixed 40 MHz LC filter; by the time I get everything out the door I'd like to be ~60dB down for all my aliases. Anyone have any recommendations on which of these I'd be better off with? Or better alternatives that I haven't considered? Or pointers to good lit on the subject? The multirate section of O&S is both short and impenetrable, Googling "FIR halfband" turns up lots of IEEE chaff and no wheat, and "multirate digital signal" on Amazon gives me dozens of books and no insight as to which are any good. Thanks, Rob -- Rob Gaddi, Highland Technology Email address is currently out of order

# Variable rate interpolation

Started by ●August 17, 2009

Reply by ●August 17, 20092009-08-17

On Aug 17, 2:35�pm, Rob Gaddi <rga...@technologyhighland.com> wrote:> I'm primarily an analog and logic designer, so please bear with my lack > of DSP chops. > > I've got an application where I'm looking to feed a DAC at a constant > 128 MSPS from a data stream that will be a power of 2 fraction of that > (64 MSPS down to 250 kSPS).and this is synchronous, right? if your input data is at 64 MSPS, then you always need to generate exactly two output samples for each input sample (no slippage), right? assuming that is the case, is it important to you that (in the case of 64 MSPS going in) that one of the output samples is exactly equal to the input sample (and thus only the other sample need be calculated)?> �I'd like to be able to get pretty close to > the Nyquist limit (say 0.4 or so) of whatever the original data rate is.this means that if your input sampling rate is 64 MSPS, then the usable bandwidth of the data is up to 0.4*64 MHz or 25.6 MHz, right? r b-j

Reply by ●August 17, 20092009-08-17

On Mon, 17 Aug 2009 16:10:01 -0700 (PDT) robert bristow-johnson <rbj@audioimagination.com> wrote:> On Aug 17, 2:35�pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > I'm primarily an analog and logic designer, so please bear with my > > lack of DSP chops. > > > > I've got an application where I'm looking to feed a DAC at a > > constant 128 MSPS from a data stream that will be a power of 2 > > fraction of that (64 MSPS down to 250 kSPS). > > and this is synchronous, right? if your input data is at 64 MSPS, > then you always need to generate exactly two output samples for each > input sample (no slippage), right? assuming that is the case, is it > important to you that (in the case of 64 MSPS going in) that one of > the output samples is exactly equal to the input sample (and thus only > the other sample need be calculated)?Yep, absolutely synchronous. There's a counter, and each bit's 1->0 transition is one input to an 8:1 mux that determines how often I pull the next sample from the FIFO. As for exact equality, it's not important. So long as the system is LTI it's good enough.> > > �I'd like to be able to get pretty close to > > the Nyquist limit (say 0.4 or so) of whatever the original data > > rate is. > > this means that if your input sampling rate is 64 MSPS, then the > usable bandwidth of the data is up to 0.4*64 MHz or 25.6 MHz, right? > > r b-j >Exactly. -- Rob -- Rob Gaddi, Highland Technology Email address is currently out of order

Reply by ●August 18, 20092009-08-18

Rob Gaddi wrote:> I'm primarily an analog and logic designer, so please bear with my lack > of DSP chops. > > I've got an application where I'm looking to feed a DAC at a constant > 128 MSPS from a data stream that will be a power of 2 fraction of that > (64 MSPS down to 250 kSPS). I'd like to be able to get pretty close to > the Nyquist limit (say 0.4 or so) of whatever the original data rate is. > It seems so far like my two primary choices for interpolating the data > up are: a) a CIC filter plus an FIR precompensator to clean up the sinc > response of the CIC, followed by a barrel shifter to get rid of the > bit growth or b) a single (or possibly a cascade of?) FIR interpolation > filters.So the max. upsampling ratio is 512; you will probably need 4 or 5 stages of interpolation for that. It could be more optimal to design the separate filter arrangements for each mode rather then use the same halfband filter for everything.> The implementation platform will be a Spartan-6 FPGA, which means my > primary DSP tool is a dedicated multiply+add block, which can of > course be configured as a multiply+accumulate. Ultimately, the DAC > feeds a fixed 40 MHz LC filter; by the time I get everything out the > door I'd like to be ~60dB down for all my aliases. > > Anyone have any recommendations on which of these I'd be better off > with?That entirely depends on your application requirements (passband flatness, stopband rejection) and the hardware capabilities. You may need to try the different variants.> Or better alternatives that I haven't considered?The IIR filters can be used as well.> Or pointers > to good lit on the subject? The multirate section of O&S is both short > and impenetrable, Googling "FIR halfband" turns up lots of IEEE chaff > and no wheat, and "multirate digital signal" on Amazon gives me dozens > of books and no insight as to which are any good.I would recommend the classic book: "Multirate Signal Processing" by Rabiner. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com

Reply by ●August 18, 20092009-08-18

On Aug 17, 8:32 pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:>Rob Gaddi wrote: >> ....> to good lit on the subject? The multirate section of O&S is both short .> and impenetrable, Googling "FIR halfband" turns up lots of IEEE chaff .> and no wheat, and "multirate digital signal" on Amazon gives me dozens .> of books and no insight as to which are any good.> > I would recommend the classic book: "Multirate Signal Processing" by > Rabiner. > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultanthttp://www.abvolt.comAvailable for free: Overview of Multirate Signal Processing Module by: Douglas L. Jones. http://cnx.org/content/m12777/latest/ Dale B. Dalrymple

Reply by ●August 18, 20092009-08-18

On Aug 17, 7:24=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote:> On Mon, 17 Aug 2009 16:10:01 -0700 (PDT) > > robert bristow-johnson <r...@audioimagination.com> wrote: > > On Aug 17, 2:35=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > > I'm primarily an analog and logic designer, so please bear with my > > > lack of DSP chops. > > > > I've got an application where I'm looking to feed a DAC at a > > > constant 128 MSPS from a data stream that will be a power of 2 > > > fraction of that (64 MSPS down to 250 kSPS). > > > and this is synchronous, right? =A0if your input data is at 64 MSPS, > > then you always need to generate exactly two output samples for each > > input sample (no slippage), right? =A0assuming that is the case, is it > > important to you that (in the case of 64 MSPS going in) that one of > > the output samples is exactly equal to the input sample (and thus only > > the other sample need be calculated)? > > Yep, absolutely synchronous. =A0There's a counter, and each bit's 1->0 > transition is one input to an 8:1 mux that determines how often I pull > the next sample from the FIFO. =A0As for exact equality, it's not > important. So long as the system is LTI it's good enough. >then my suggestion is a simple 2-phase FIR interpolator that interpolates 1/4 sample behind the "current sample" (which, to be causal, is a fixed delay behind the actual real-time current sample) and 1/4 sample ahead of the "current sample". the two FIR impulse responses for the 2 phases are identical except one is in reverse order compared to the other. that way they have identical magnitude frequency response (which you would not get if you had a delay of 0 and 1/2 sample). if your design was by use of window functions (not the best, parks-mcclellan might be better, but a kaiser window ain't too bad), then the non-causal impulse responses might look like: g[n] =3D sinc(n - 1/4) * w(n-1/4) and h[n] =3D sinc(n + 1/4) * w(n+1/4) where the window function, w(t), has even symmetry: w(-t) =3D w(t). note that g[-n] =3D h[n]. so this creates two samples, spaced apart by 1/2 sample, for every sample going in. use this interpolation recursively for every doubling of the sampling rate. i dunno, it might work. r b-j

Reply by ●August 28, 20092009-08-28

On Mon, 17 Aug 2009 22:32:57 -0500 Vladimir Vassilevsky <nospam@nowhere.com> wrote:> > > Rob Gaddi wrote: > > I'm primarily an analog and logic designer, so please bear with my > > lack of DSP chops. > > > > I've got an application where I'm looking to feed a DAC at a > > constant 128 MSPS from a data stream that will be a power of 2 > > fraction of that (64 MSPS down to 250 kSPS). I'd like to be able > > to get pretty close to the Nyquist limit (say 0.4 or so) of > > whatever the original data rate is. It seems so far like my two > > primary choices for interpolating the data up are: a) a CIC filter > > plus an FIR precompensator to clean up the sinc response of the > > CIC, followed by a barrel shifter to get rid of the bit growth or > > b) a single (or possibly a cascade of?) FIR interpolation filters. > > So the max. upsampling ratio is 512; you will probably need 4 or 5 > stages of interpolation for that. It could be more optimal to design > the separate filter arrangements for each mode rather then use the > same halfband filter for everything. > > > The implementation platform will be a Spartan-6 FPGA, which means my > > primary DSP tool is a dedicated multiply+add block, which can of > > course be configured as a multiply+accumulate. Ultimately, the DAC > > feeds a fixed 40 MHz LC filter; by the time I get everything out the > > door I'd like to be ~60dB down for all my aliases. > > > > Anyone have any recommendations on which of these I'd be better off > > with? > > That entirely depends on your application requirements (passband > flatness, stopband rejection) and the hardware capabilities. You may > need to try the different variants. > > > Or better alternatives that I haven't considered? > > The IIR filters can be used as well. > > > Or pointers > > to good lit on the subject? The multirate section of O&S is both > > short and impenetrable, Googling "FIR halfband" turns up lots of > > IEEE chaff and no wheat, and "multirate digital signal" on Amazon > > gives me dozens of books and no insight as to which are any good. > > I would recommend the classic book: "Multirate Signal Processing" by > Rabiner. > > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultant > http://www.abvolt.comThanks, everyone, for the help. Vladmir, you were right about Crochiere & Rabiner. The book was a pain to hunt down, but I just put away 100+ pages of it last night and it's really very well done. -- Rob Gaddi, Highland Technology Email address is currently out of order